(1) Field of the Invention
The present invention relates to a semiconductor device and a manufacturing method of the same.
(2) Description of the Related Art
In recent electronic devices, a number of semiconductor devices using a wafer level chip size package (CSP) method that is an assembly process performed during a wafer state have been used in order to achieve further reduction in size, thickness, and weight as well as higher-density packaging of an electronic device.
For example, a solid-state imaging device that is a representative optical device is used as a light-receiving sensor in a digital imaging device such as a digital still camera, a cell phone camera, and a digital video camera. To realize further reduction in size, thickness, and weight as well as higher-density packaging of imaging devices in recent years, a wafer level CSP method has been adopted that is a method for securing electrical connection inside and outside a device by forming a through electrode and rewiring during assembly at a wafer level before singulation, instead of the forming and rewiring during ceramic-type or plastic-type packaging in which the electrical connection inside and outside the device is secured by die bonding or wire bonding (for example, see Japanese Unexamined Patent Application Publication 2004-207461 and Japanese Unexamined Patent Application Publication 2007-123909).
FIG. 1 is a cross-sectional view of a solid-state imaging device having a conventional wafer level CSP configuration.
As shown in FIG. 1, a conventional solid-state imaging device 100A includes: an imaging area 102 formed on a semiconductor substrate 101 and having a main surface which is a light-receiving surface of the semiconductor substrate 101 and on which a plurality of microlenses 103 are provided; a peripheral circuit area 104A formed in a perimeter region of the imaging area 102 on the main surface; and a solid-state imaging element 100 including a plurality of electrode portions 104B connected to the peripheral circuit area 104A.
In addition, on a main-surface side of the semiconductor substrate 101, a transparent substrate 106 formed of, for example, optical glass is formed via an adhesive material 105 made primarily of resin. Furthermore, inside the semiconductor substrate 101, a through electrode 107 penetrating through the semiconductor substrate 101 in a thickness direction is formed.
In the back surface opposite to the main surface of the semiconductor substrate 101, metal wiring 108 connected to the plurality of electrode portions 104B that are connected to the peripheral circuit area 104A is formed via the through electrode 107, and an insulating resin layer 109 is formed to have an aperture 110 which covers a portion of the metal wiring 108 and exposes the other portion of the metal wiring 108. In the aperture 110, an external electrode 111 made of, for example, a solder material is formed.
Note that the solid-state imaging element 100 is electrically insulated from the through electrode 107 and the metal wiring 108 by an insulation layer not shown in the figure.
As described above, in the conventional solid-state imaging device 100A, the plurality of electrode portions 104B are electrically connected to the metal wiring 108 via the through electrode 107, and furthermore are electrically connected to an external electrode 111 via the metal wiring 108, thus allowing extraction of the light reception signal.
The conventional solid-state imaging device 100A described above is manufactured by the following processing, for example.
(Process 1) First, a plurality of the solid-state imaging elements 100 having the configuration described above are formed on the wafer according to a well-known method. To the wafer on which the plurality of solid-state imaging elements 100 are formed, the transparent substrate 106 having the same shape as the wafer and made of, for example, optical glass and so on is attached via the adhesive material 105 made primarily of a resin layer.
(Process 2) Next, a through hole, which penetrates through the semiconductor substrate from a back side and exposes the plurality of electrode portions 104B connected to the peripheral circuit area 104A, is formed using dry etching, wet etching, or the like. Subsequently, by embedding a conductive material in the through hole, the through electrode 107 to be connected to the plurality of electrode portions 104B which extracts light reception signal is formed.
(Process 3) Next, by electrolytic plating, the metal wiring 108 to be electrically connected to the through electrode 107 is formed on the back surface of the solid-state imaging element 100.
(Process 4) Next, on the back surface of the solid-state imaging element 100, the insulating resin layer 109 is formed to cover the metal wiring 108. Generally, the insulating resin layer 109 is formed using a photosensitive resin, by spin coating or attaching dry film.
(Process 5) Subsequently, by selectively removing the insulating resin layer 109, using a photolithography technique (exposure and development), the aperture 110 exposing a portion of the metal wiring 108 is formed.
(Process 6) Subsequently, in the aperture 110, by solder ball placement or solder paste printing using flux, an external electrode 111 is formed of, for example, a solder material, and is to be electrically connected to the metal wiring 108.
(Process 7) Lastly, the wafer is singulated into a plurality of solid-state imaging devices 100A as shown in FIG. 1, by cutting the solid-state imaging element 100, the adhesive material 105, the transparent substrate 106, and the insulating resin layer 109 all at once, using a cutting tool, for example, a dicing saw.